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Description of  DIGITAL ELECTRONICS: Beginner Guide

DIGITAL ELECTRONICS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9 Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions Minterm - Maxterm - Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions Quine - McCluskey method of minimization. AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR Implementations of Logic Functions using gates, NANDNOR implementations Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates 9 Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/ Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder parity checker parity generators code converters Magnitude Comparator. 9 Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters 9 Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM, RAM RAM organization Write operation Read operation Memory cycle - Timing wave forms Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) - Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL. General Model Classification Design Use of Algorithmic State Machine Analysis of Synchronous Sequential Circuits Design of fundamental mode and pulse mode circuits Incompletely specified State Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG. Read more